- Developing rule and runs for IC verification tools
- Creating run sets for different variant from Foundry document
- Creating PCELL/Pycell for basic devices for various CAD software’s
- Verifying run sets against deliverable criteria
- Qualification BE/ B.Tech (Electronics) , ME/ M.Tech ( VLSI Domain )
- IC Layout experience |0-2 Yrs
- Perl/Skill/python/shell knowledge.
- Quick learner.
- PCELL | LVS & DRC Deck development.
- Good understanding of each phase of IC design flow.
- Knowledge of verification cad software I.E. Caliber, PVS, Assura, ICV
- Good in programming concepts and Data structure